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2009
ASIC functional Verification


K Gopi Krishna
www.testbench.in
1/1/2009

January 1, 2009 [ASIC FUNCTIONAL VERIFICATION]


Preface

What is this document about?
This document is all about functional verification examples - examples -
examples. This document is a reflection of my 2 years of experience in Verification.
Everything I learned (learn) about SystemVerilog was(will be) presented in this
document. Making of this document is a continuous effort. I update this document
whenever I get time. You can always get the up-to-date version from at
www.testbench.in.


Who should read this Document?
This Document is for both Beginner and Intermediate Verification-Engineers who
wants to learn full functional flow of Verification and start writing testbenchs. Every topic
is explained with detailed example(s) and ready to simulate without a single
modification. All the examples are self explanatory and explore the real intention of the
construct in the language. Simulation log is provided for examples where it is needed.
User will be more benefitted by simulating examples and playing with them. Some
examples go deep in to the hidden corners of the language.
For experienced engineers, this Document can be a great reference to explore
many SystemVerilog constructs with some fine Examples. Search for the construct,
copy the example, tweak it and learn it.
- Gopi Krishna





January 1, 2009 [ASIC FUNCTIONAL VERIFICATION]


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